library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONV_STD_DIR is
    port(
         clk: in std_logic;
         Xstd: in std_logic;
	 		Ystd: in std_logic_vector(34 downto 0);
	 		Zstd: in std_logic_vector(34 downto 0);
	 		Ydir: out std_logic_vector(8 downto 0);
	 		Zdir: out std_logic_vector(8 downto 0)
   	);
end CONV_STD_DIR;

-- Esto lo unico que hace es esta cuenta (si X>0):
--160+160*Y
--160-160*Z

--160*Y=Y&"0000"/1000000000=(Y&"0000")*275/274877906944


architecture Convertir of CONV_STD_DIR is
begin
   process(clk)
       constant N275: std_logic_vector(8 downto 0):="100010011";
       variable M: std_logic_vector(37 downto 0);
       variable prod: std_logic_vector(46 downto 0);
   begin
       if rising_edge(clk) then
           if Xstd='0' then
               if Ystd(34)='0' then
                  M:=Ystd(33 downto 0)&"0000";
               else
                  M:=(not(Ystd(33 downto 0))+1)&"0000";
               end if;
               prod:=("000000000"&M)+("00000000"&M&'0')+("00000"&M&"0000")+('0'&M&"00000000");--prod:=M*N275;
               if Ystd(34)='0' then
                  Ydir <= "010100000" + prod(46 downto 38);
               else 
                  Ydir <= "010100000" - prod(46 downto 38);
               end if;
               if Zstd(34)='0' then
                  M:=Zstd(33 downto 0)&"0000";
               else
                  M:=(not(Zstd(33 downto 0))+1)&"0000";
               end if;
               prod:=("000000000"&M)+("00000000"&M&'0')+("00000"&M&"0000")+('0'&M&"00000000");--prod:=M*N275;
               if Zstd(34)='0' then
                  Zdir <= "010100000" - prod(46 downto 38);
               else 
                  Ydir <= "010100000" + prod(46 downto 38);
               end if;
           end if;
       end if;
   end process;
end Convertir; 
